115 search results - page 20 / 23 » Topological Design of Interconnected LAN-MAN Networks |
103
Voted
ISCA
2007
IEEE
15 years 8 months ago
2007
IEEE
We introduce a novel chip fabrication technique called “brick and mortar”, in which chips are made from small, pre-fabricated ASIC bricks and bonded in a designer-specified a...
113
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DAC
2006
ACM
15 years 5 months ago
2006
ACM
Conventionally, signal net routing is almost always implemented as Steiner trees. However, non-tree topology is often superior on timing performance as well as tolerance to open f...
101
Voted
DAC
1996
ACM
15 years 6 months ago
1996
ACM
: In a high performance microprocessor such as Digital's 300MHz Alpha 21164, the distribution of a high quality clock signal to all regions of the device is achieved using a c...
84
Voted
ENTCS
2008
15 years 1 months ago
2008
A Network-on-Chip (NoC) is increasingly needed to interconnect the large number and variety of Intellectual Property (IP) cells that make up a System-on-Chip (SoC). The network mu...
109
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TCAD
2008
15 years 1 months ago
2008
Abstract--Advances in very large-scale integration technology make clock skew more susceptible to process variations. Notwithstanding efficient exact zero-skew algorithms, clock sk...