26 search results - page 4 / 6 » Total Power Minimization in Glitch-Free CMOS Circuits Consid... |
107
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TVLSI
2008
15 years 1 months ago
2008
-- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold a...
105
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ISCAS
2003
IEEE
15 years 7 months ago
2003
IEEE
The width of an interconnect line a ects the total power consumed by a circuit. A tradeo exists, however, between the dynamic power and the short-circuit power in determining the ...
157
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FPGA
2003
ACM
15 years 7 months ago
2003
ACM
This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but...
ICCAD
2007
IEEE
15 years 10 months ago
2007
IEEE
Timing budgeting under process variations is an important step in a statistical optimization flow. We propose a novel formulation of the problem where budgets are statistical ins...
102
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GLVLSI
2006
IEEE
15 years 7 months ago
2006
IEEE
A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...