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76
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ISCA
2003
IEEE
96views Hardware» more  ISCA 2003»
15 years 5 months ago
Parallelism in the Front-End
As processor back-ends get more aggressive, front-ends will have to scale as well. Although the back-ends of superscalar processors have continued to become more parallel, the fro...
Paramjit S. Oberoi, Gurindar S. Sohi
97
Voted
TVLSI
1998
80views more  TVLSI 1998»
15 years 3 days ago
Power optimization of core-based systems by address bus encoding
— This paper presents a solution to the problem of reducing the power dissipated by a digital system containing an intellectual proprietary core processor which repeatedly execut...
Luca Benini, Giovanni De Micheli, Enrico Macii, Ma...
HPDC
2007
IEEE
15 years 6 months ago
Feedback-directed thread scheduling with memory considerations
This paper describes a novel approach to generate an optimized schedule to run threads on distributed shared memory (DSM) systems. The approach relies upon a binary instrumentatio...
Fengguang Song, Shirley Moore, Jack Dongarra
LCTRTS
2000
Springer
15 years 4 months ago
Reordering Memory Bus Transactions for Reduced Power Consumption
Low energy consumption is becoming the primary design consideration for battery-operated and portable embedded systems, such as personal digital assistants, digital still and movi...
Bruce R. Childers, Tarun Nakra
92
Voted
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
15 years 6 months ago
Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach
— A novel power attack resistant cryptosystem is presented in this paper. Security in digital computing and communication is becoming increasingly important. Design techniques th...
Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan,...