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90
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MICRO
2000
IEEE
98views Hardware» more  MICRO 2000»
15 years 3 months ago
The store-load address table and speculative register promotion
Register promotion is an optimization that allocates a value to a register for a region of its lifetime where it is provably not aliased. Conventional compiler analysis cannot alw...
Matt Postiff, David Greene, Trevor N. Mudge
80
Voted
PLDI
2003
ACM
15 years 4 months ago
Taming the IXP network processor
We compile Nova, a new language designed for writing network processing applications, using a back end based on integer-linear programming (ILP) for register allocation, optimal b...
Lal George, Matthias Blume
71
Voted
EUROMICRO
1999
IEEE
15 years 3 months ago
Delft-Java Dynamic Translation
This paper describes the DELFT-JAVA processor and the mechanisms required to dynamically translate JVM instructions into DELFT-JAVA instructions. Using a form of hardware register...
C. John Glossner, Stamatis Vassiliadis
DAC
1996
ACM
15 years 3 months ago
A Register File and Scheduling Model for Application Specific Processor Synthesis
In this paper, we outline general design steps of our synthesis tool to realize application specific co-processors such that for a given scientific application having intensive ite...
Ehat Ercanli, Christos A. Papachristou
CC
2009
Springer
153views System Software» more  CC 2009»
15 years 11 months ago
Register Spilling and Live-Range Splitting for SSA-Form Programs
Register allocation decides which parts of a variable's live range are held in registers and which in memory. The compiler inserts spill code to move the values of variables b...
Matthias Braun, Sebastian Hack