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82
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IISWC
2008
IEEE
15 years 3 months ago
STAMP: Stanford Transactional Applications for Multi-Processing
Abstract—Transactional Memory (TM) is emerging as a promising technology to simplify parallel programming. While several TM systems have been proposed in the research literature,...
Chi Cao Minh, JaeWoong Chung, Christos Kozyrakis, ...
89
Voted
MICRO
2010
IEEE
170views Hardware» more  MICRO 2010»
14 years 7 months ago
Tolerating Concurrency Bugs Using Transactions as Lifeguards
Abstract--Parallel programming is hard, because it is impractical to test all possible thread interleavings. One promising approach to improve a multi-threaded program's relia...
Jie Yu, Satish Narayanasamy
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
12 years 12 months ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar
IPPS
2010
IEEE
14 years 6 months ago
Efficient hardware support for the Partitioned Global Address Space
We present a novel architecture of a communication engine for non-coherent distributed shared memory systems. The shared memory is composed by a set of nodes exporting their memory...
Holger Fröning, Heiner Litz
75
Voted
VLDB
1992
ACM
83views Database» more  VLDB 1992»
15 years 1 months ago
A Performance Study of Alternative Object Faulting and Pointer Swizzling Strategies
This paper presents a portable, efficient method for accessing memory resident persistent objects in virtual memory in the context of the E programming language. Under the approac...
Seth J. White, David J. DeWitt