1640 search results - page 185 / 328 » Transistor-Level Timing Analysis Using Embedded Simulation |
107
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IJON
2007
15 years 3 months ago
2007
In the real world, visual information is selected over time as well as space, when we prioritise new stimuli for attention. Watson and Humphreys [Visual marking: prioritising sele...
134
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EMSOFT
2009
Springer
15 years 10 months ago
2009
Springer
Scratchpads have been widely proposed as an alternative to caches for embedded systems. Advantages of scratchpads include reduced energy consumption in comparison to a cache and a...
138
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ISCA
2007
IEEE
15 years 9 months ago
2007
IEEE
The recently released SPEC CPU2006 benchmark suite is expected to be used by computer designers and computer architecture researchers for pre-silicon early design analysis. Partia...
109
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DATE
2006
IEEE
15 years 9 months ago
2006
IEEE
— In this paper, we present an analysis methodology to compute circuit node sensitivity due to charged particle induced delay (timing) errors, Soft Delay Errors (SDE). We define...
101
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CDC
2009
IEEE
15 years 8 months ago
2009
IEEE
— A promising approach for ultra high data storage capacities in magnetic hard disk drives is the use of bitpatterned media (BPM) that allows both higher track densities and incr...