1640 search results - page 68 / 328 » Transistor-Level Timing Analysis Using Embedded Simulation |
114
Voted
DATE
2008
IEEE
15 years 9 months ago
2008
IEEE
Shrinking feature sizes and process variations are of increasing concern in modern technology. It is urgent that we develop statistical interconnect timing models which are harmon...
110
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IOR
2008
15 years 2 months ago
2008
We consider the risk of a portfolio comprised of loans, bonds, and financial instruments that are subject to possible default. In particular, we are interested in performance meas...
128
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JCST
2010
14 years 9 months ago
2010
Probabilistic techniques are widely used in the analysis of algorithms to estimate the computational complexity of algorithms or a computational problem. Traditionally, such analys...
130
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ECRTS
2008
IEEE
15 years 9 months ago
2008
IEEE
The commonly used task models for real-time systems focus on execution windows expressing earliest start times and deadlines of tasks for feasibility. Within these windows, execut...
129
Voted
SAMOS
2009
Springer
15 years 9 months ago
2009
Springer
Abstract. Memory access latency can limit microcontroller system performance. SDRAM access control policies impact latency through SDRAM device state. It is shown that execution ti...