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» Transistor-Level Timing Analysis Using Embedded Simulation
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DAC
2004
ACM
16 years 3 months ago
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
With deep-sub-micron (DSM) technology, statistical timing analysis becomes increasingly crucial to characterize signal transmission over global interconnect wires. In this paper, ...
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
FMSD
2006
131views more  FMSD 2006»
15 years 2 months ago
Specification and analysis of the AER/NCA active network protocol suite in Real-Time Maude
This paper describes the application of the Real-Time Maude tool and the Maude formal methodology to the specification and analysis of the AER/NCA suite of active network multicast...
Peter Csaba Ölveczky, José Meseguer, C...
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DAC
2008
ACM
16 years 3 months ago
Driver waveform computation for timing analysis with multiple voltage threshold driver models
This paper introduces an accurate and efficient electrical analysis of logic gates modeled as Multiple Voltage Threshold Models (MVTM) loaded by the associated interconnect. MVTMs...
Peter Feldmann, Soroush Abbaspour, Debjit Sinha, G...
IFIPTCS
2000
15 years 6 months ago
Masaccio: A Formal Model for Embedded Components
Masaccio is a formal model for hybrid dynamical systems which are built from atomic discrete components (di erence equations) and atomic continuous components (di erential equation...
Thomas A. Henzinger
RTAS
2005
IEEE
15 years 8 months ago
Hybrid Supervisory Utilization Control of Real-Time Systems
Feedback control real-time scheduling (FCS) aims at satisfying performance specifications of real-time systems based on adaptive resource management. Existing FCS algorithms often...
Xenofon D. Koutsoukos, Radhika Tekumalla, Balachan...