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70
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ISCA
2009
IEEE
148views Hardware» more  ISCA 2009»
15 years 4 months ago
Memory mapped ECC: low-cost error protection for last level caches
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
Doe Hyun Yoon, Mattan Erez
TCGOV
2005
Springer
15 years 3 months ago
Participatory Budget Formation Through the Web
Abstract. We describe a web-based system to support groups in elaborating participatory budgets. Rather than using physical meetings with voting mechanisms, we promote virtual meet...
Jesus Rios, David Ríos Insua, E. Fernandez,...
103
Voted
MICRO
2003
IEEE
258views Hardware» more  MICRO 2003»
15 years 3 months ago
LLVA: A Low-level Virtual Instruction Set Architecture
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...
Vikram S. Adve, Chris Lattner, Michael Brukman, An...
90
Voted
ISMB
1993
14 years 11 months ago
Pattern Discovery in Gene Regulation: Designing an Analysis Environment
Interactions that determinecellular fate are exceedingly complex, can take place at different levels of gene regulation and involve a large numberof components(such as genes, prot...
Stella Veretnik, Bruce R. Schatz
CORR
2010
Springer
119views Education» more  CORR 2010»
14 years 9 months ago
Report on the XBase Project
This project addressed the conceptual fundamentals of data storage, investigating techniques for provision of highly generic storage facilities that can be tailored to produce var...
Evangelos Zirintsis, Graham N. C. Kirby, Alan Dear...