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» Trusted Design in FPGAs
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FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
15 years 2 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor
IPPS
2007
IEEE
15 years 4 months ago
Pseudo Trust: Zero-Knowledge Based Authentication in Anonymous Peer-to-Peer Protocols
Most of the current trust models in peer-to-peer (P2P) systems are identity based, which means that in order for one peer to trust another, it needs to know the other peer’s ide...
Li Lu, Jinsong Han, Lei Hu, Jinpeng Huai, Yunhao L...
VLSID
2007
IEEE
92views VLSI» more  VLSID 2007»
15 years 10 months ago
Floorplanning in Modern FPGAs
State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for oor...
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
ISCAS
2003
IEEE
112views Hardware» more  ISCAS 2003»
15 years 3 months ago
Architectures for function evaluation on FPGAs
This paper presents a new family of architectures for multi-cycle area-efficient evaluation of elementary and composite functions, and an exploration of the design tradeoffs for i...
Nalin Sidahao, George A. Constantinides, Peter Y. ...
IPPS
2002
IEEE
15 years 2 months ago
JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGAs
Reconfigurable computing based on partial reconfiguration of field programmable gate arrays (FPGAs) is yet to move to the mainstream of computing. Hardware devices that support su...
Anup Kumar Raghavan, Peter Sutton