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ICCAD
2007
IEEE
87views Hardware» more  ICCAD 2007»
15 years 7 months ago
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design
—Register allocation, in high-level synthesis and ASIP design, is the process of determining the number of registers to include in the resulting circuit or processor. The goal is...
Philip Brisk, Ajay K. Verma, Paolo Ienne
CSMR
2008
IEEE
15 years 4 months ago
Package Reference Fingerprint: a Rich and Compact Visualization to Understand Package Relationships
Object-oriented languages such as Java, Smalltalk, and C++ structure their programs using packages, allowing classes to be organized into named abstractions. Maintainers of large ...
Hani Abdeen, Ilham Alloui, Stéphane Ducasse...
84
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ISAAC
2005
Springer
123views Algorithms» more  ISAAC 2005»
15 years 3 months ago
Sampling Unlabeled Biconnected Planar Graphs
We present an expected polynomial time algorithm to generate a 2-connected unlabeled planar graph uniformly at random. To do this we first derive recurrence formulas to count the ...
Manuel Bodirsky, Clemens Gröpl, Mihyun Kang
BMCBI
2008
163views more  BMCBI 2008»
14 years 10 months ago
ProfileGrids as a new visual representation of large multiple sequence alignments: a case study of the RecA protein family
Background: Multiple sequence alignments are a fundamental tool for the comparative analysis of proteins and nucleic acids. However, large data sets are no longer manageable for v...
Alberto I. Roca, Albert E. Almada, Aaron C. Abajia...
POPL
2003
ACM
15 years 10 months ago
Bitwidth aware global register allocation
Multimedia and network processing applications make extensive use of subword data. Since registers are capable of holding a full data word, when a subword variable is assigned a r...
Sriraman Tallam, Rajiv Gupta