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139
Voted
TC
1998
15 years 3 months ago
Optimizing the Instruction Cache Performance of the Operating System
—High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...
Josep Torrellas, Chun Xia, Russell L. Daigle
DEXAW
2000
IEEE
160views Database» more  DEXAW 2000»
15 years 8 months ago
An Adaptive AVI-Based Cache Invalidation Scheme for Mobile Computing Systems
In a mobile computing system, caching data items at the mobile clients is important to reduce the data access delay in a unreliable and low bandwidth mobile network. However, effi...
Joe Chun-Hung Yuen, Edward Chan, Kam-yiu Lam, Hei-...
PDPTA
2003
15 years 5 months ago
Tuxedo: A Peer-to-Peer Caching System
We are witnessing two trends in Web content access: (a) increasing amounts of dynamic and personalized Web content, and (b) a significant growth in “on-the-move” access using...
Weisong Shi, Kandarp Shah, Yonggen Mao, Vipin Chau...
161
Voted
DAC
2009
ACM
15 years 8 months ago
Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators
Dynamic binary translation (DBT) can be used to address important issues in embedded systems. DBT systems store translated code in a software-managed code cache. Unlike general-pu...
José Baiocchi, Bruce R. Childers
137
Voted
TC
1998
15 years 3 months ago
Design Verification of the S3.mp Cache-Coherent Shared-Memory System
—This paper describes the methods used to formulate and validate the memory subsystem of the cache-coherent Sun Scalable emory MultiProcessor (S3.mp) at three levels of abstracti...
Fong Pong, Michael C. Browne, Gunes Aybay, Andreas...