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» Uncertainty Reduction Using Dynamics
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116
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ISCAS
2005
IEEE
103views Hardware» more  ISCAS 2005»
15 years 8 months ago
Why area might reduce power in nanoscale CMOS
— In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reducti...
Paul Beckett, S. C. Goldstein
105
Voted
ASPDAC
2005
ACM
134views Hardware» more  ASPDAC 2005»
15 years 8 months ago
Wire congestion and thermal aware 3D global placement
— The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wirelength. However, wire congestion and thermal issues are exacerbated d...
Karthik Balakrishnan, Vidit Nanda, Siddharth Easwa...
DATE
2003
IEEE
109views Hardware» more  DATE 2003»
15 years 7 months ago
A Novel Metric for Interconnect Architecture Performance
We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given...
Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Mud...
CP
2001
Springer
15 years 7 months ago
A General Scheme for Multiple Lower Bound Computation in Constraint Optimization
Abstract. Computing lower bounds to the best-cost extension of a tuple is an ubiquous task in constraint optimization. A particular case of special interest is the computation of l...
Rina Dechter, Kalev Kask, Javier Larrosa
119
Voted
ICWS
2010
IEEE
15 years 4 months ago
Extending BPMN for Supporting Customer-Facing Service Quality Requirements
Service-oriented computing promises to create flexible business processes and applications on demand by dynamically assembling loosely coupled services within and across organizati...
Kawther Saeedi, Liping Zhao, Pedro R. Falcone Samp...