1217 search results - page 102 / 244 » Uncertainty-aware circuit optimization |
ASYNC
2005
IEEE
15 years 5 months ago
2005
IEEE
This paper proposes applying a logic synthesis approach to high level synthesis from SpecC specifications to timed asynchronous gate-level circuits. The state-based logic synthes...
CEC
2003
IEEE
15 years 4 months ago
2003
IEEE
In this paper, the use of Simulated Evolution (SimE) Algorithm in the design of digital logic circuits is proposed. SimE algorithm consists of three steps: evaluation, selection an...
DATE
2002
IEEE
15 years 4 months ago
2002
IEEE
Production test costs for today’s RF circuits are rapidly escalating. Two factors are responsible for this cost escalation: (a) the high cost of RF ATEs and (b) long test times ...
DAC
2002
ACM
16 years 9 days ago
2002
ACM
A regular circuit structure called a River PLA and its reconfigurable version, Glacier PLA, are presented. River PLAs provide greater regularity than circuits implemented with sta...
CEC
2005
IEEE
15 years 5 months ago
2005
IEEE
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...