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» Uncertainty-aware circuit optimization
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DATE
2009
IEEE
163views Hardware» more  DATE 2009»
15 years 6 months ago
Fixed points for multi-cycle path detection
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...
Vijay D'Silva, Daniel Kroening
DATE
1999
IEEE
102views Hardware» more  DATE 1999»
15 years 3 months ago
Minimal Length Diagnostic Tests for Analog Circuits using Test History
In this paper we propose an efficient transient test generation method to comprehensively test analog circuits using minimum test time. A divide and conquer strategy is formulated...
Alfred V. Gomes, Abhijit Chatterjee
ICCAD
2007
IEEE
109views Hardware» more  ICCAD 2007»
15 years 8 months ago
Inductive equivalence checking under retiming and resynthesis
Retiming and resynthesis are among the most important techniques for practical sequential circuit optimization. However, their applicability is much limited due to verification c...
Jie-Hong Roland Jiang, Wei-Lun Hung
ISPD
2009
ACM
127views Hardware» more  ISPD 2009»
15 years 6 months ago
Synthesizing a representative critical path for post-silicon delay prediction
Several approaches to post-silicon adaptation require feedback from a replica of the nominal critical path, whose variations are intended to reflect those of the entire circuit a...
Qunzeng Liu, Sachin S. Sapatnekar
DATE
2003
IEEE
108views Hardware» more  DATE 2003»
15 years 4 months ago
Generalized Posynomial Performance Modeling
This paper presents a new method to automatically generate posynomial symbolic expressions for the performance characteristics of analog integrated circuits. The coefficient set ...
Tom Eeckelaert, Walter Daems, Georges G. E. Gielen...