1217 search results - page 151 / 244 » Uncertainty-aware circuit optimization |
TVLSI
2010
14 years 6 months ago
2010
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
ICCAD
2006
IEEE
15 years 8 months ago
2006
IEEE
The existing work on via-stapling in 3D integrated circuits optimizes power and thermal integrity separately and uses steadystate thermal analysis. This paper presents the first ...
BMCBI
2007
14 years 11 months ago
2007
Background: To infer homology and subsequently gene function, the Smith-Waterman (SW) algorithm is used to find the optimal local alignment between two sequences. When searching s...
DAC
2000
ACM
16 years 19 days ago
2000
ACM
Joint module selection and retiming is a powerful technique to optimize the implementation cost and the speed of a circuit specified using a synchronous data-flow graph (DFG). In ...
ISPD
2009
ACM
15 years 6 months ago
2009
ACM
Gate sizing and threshold voltage (Vt) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivity-driven h...