Sciweavers

1217 search results - page 177 / 244
» Uncertainty-aware circuit optimization
Sort
View
IACR
2011
94views more  IACR 2011»
14 years 3 months ago
Secure Computation with Sublinear Amortized Work
Traditional approaches to secure computation begin by representing the function f being computed as a circuit. For any function f that depends on each of its inputs, this implies ...
S. Dov Gordon, Jonathan Katz, Vladimir Kolesnikov,...
DAC
2012
ACM
13 years 6 months ago
Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs
In this work, we propose a fast and accurate chip/package thermomechanical stress and reliability co-analysis tool for TSV-based 3D ICs. We also present a design optimization meth...
Moongon Jung, David Z. Pan, Sung Kyu Lim
114
Voted
ISQED
2006
IEEE
147views Hardware» more  ISQED 2006»
15 years 10 months ago
Compact Reduced Order Modeling for Multiple-Port Interconnects
— In this paper, we propose an efficient model order reduction (MOR) algorithm, called MTermMOR, for modeling interconnect circuits with large number of external ports. The prop...
Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng ...
152
Voted
FCCM
2005
IEEE
139views VLSI» more  FCCM 2005»
15 years 9 months ago
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
ISPD
2005
ACM
151views Hardware» more  ISPD 2005»
15 years 9 months ago
Thermal via placement in 3D ICs
As thermal problems become more evident, new physical design paradigms and tools are needed to alleviate them. Incorporating thermal vias into integrated circuits (ICs) is a promi...
Brent Goplen, Sachin S. Sapatnekar