1217 search results - page 22 / 244 » Uncertainty-aware circuit optimization |
DAC
1994
ACM
15 years 1 months ago
1994
ACM
Manufacturing disturbances are inevitable in the fabrication of integrated circuits. These disturbances will result in variations in the delay speci cations of manufactured circui...
CDC
2009
IEEE
15 years 2 months ago
2009
IEEE
Abstract— A broad class of problems in circuits, electromagnetics, and optics can be expressed as finding some parameters of a linear system with a specific type. This paper is...
ISCAS
1994
IEEE
15 years 1 months ago
1994
IEEE
This paper addresses the problem of minimizing the clock period of a circuit by optimizingthe clock skews. We incorporate uncertainty factors and present a formulation that ensure...
DAC
1997
ACM
15 years 1 months ago
1997
ACM
We present a novel technique CLIP for optimizing both the height and width of CMOS cell layouts in the two-dimensional (2D) style. CLIP is based on integer-linear programming (ILP...
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Voted
ISMVL
2010
IEEE
15 years 1 months ago
2010
IEEE
—Using EXOR gates in logic synthesis often results in smaller circuit realizations. While in AND/OR synthesis the problem definition is clear, in AND/EXOR synthesis several clas...