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» Uncertainty-aware circuit optimization
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JUCS
2007
102views more  JUCS 2007»
14 years 11 months ago
The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation
: This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining ...
Oscar Pérez, Yves Berviller, Camel Tanougas...
ASPDAC
2007
ACM
89views Hardware» more  ASPDAC 2007»
15 years 3 months ago
Fast Electrical Correction Using Resizing and Buffering
Current design methodologies are geared towards meeting different design criteria, such as delay, area or power. However, in order to correctly identify the critical parts of a cir...
Shrirang K. Karandikar, Charles J. Alpert, Mehmet ...
DAC
1996
ACM
15 years 3 months ago
Use of Sensitivities and Generalized Substrate Models in Mixed-Signal IC Design
A novel methodology for circuit design and automatic layout generation is proposed for a class of mixed-signal circuits in presence of layout parasitics and substrate induced nois...
Paolo Miliozzi, Iasson Vassiliou, Edoardo Charbon,...
SODA
2012
ACM
235views Algorithms» more  SODA 2012»
13 years 1 months ago
Fast zeta transforms for lattices with few irreducibles
We investigate fast algorithms for changing between the standard basis and an orthogonal basis of idempotents for M¨obius algebras of finite lattices. We show that every lattice...
Andreas Björklund, Mikko Koivisto, Thore Husf...
FPGA
2006
ACM
113views FPGA» more  FPGA 2006»
15 years 2 months ago
Optimality study of logic synthesis for LUT-based FPGAs
Abstract--Field-programmable gate-array (FPGA) logic synthesis and technology mapping have been studied extensively over the past 15 years. However, progress within the last few ye...
Jason Cong, Kirill Minkovich