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» Uncertainty-aware circuit optimization
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IJFCS
2006
82views more  IJFCS 2006»
14 years 11 months ago
Routing Multiple Width Communications on the Circuit Switched Tree
Dynamically reconfigurable architectures offer extremely fast solutions to various problems. The Circuit Switched Tree (CST) is an important interconnect used to implement such ar...
Krishnendu Roy, Ramachandran Vaidyanathan, Jerry L...
ISLPED
1997
ACM
83views Hardware» more  ISLPED 1997»
15 years 3 months ago
A symbolic algorithm for low-power sequential synthesis
We present an algorithm that restructures the state transition graph STG of a sequential circuit so as to reduce power dissipation. The STG is modi ed without changing the behav...
Balakrishna Kumthekar, In-Ho Moon, Fabio Somenzi
ICCAD
1995
IEEE
113views Hardware» more  ICCAD 1995»
15 years 2 months ago
Logic decomposition during technology mapping
—A problem in technology mapping is that the quality of the final implementation depends significantly on the initially provided circuit structure. This problem is critical, es...
Eric Lehman, Yosinori Watanabe, Joel Grodstein, He...
GECCO
2006
Springer
143views Optimization» more  GECCO 2006»
15 years 2 months ago
A hybridized genetic parallel programming based logic circuit synthesizer
Genetic Parallel Programming (GPP) is a novel Genetic Programming paradigm. Based on the GPP paradigm and a local search operator - FlowMap, a logic circuit synthesizing system in...
Wai Shing Lau, Kin-Hong Lee, Kwong-Sak Leung
66
Voted
DAC
2009
ACM
15 years 5 months ago
Yield-driven iterative robust circuit optimization algorithm
This paper proposes an equation-based multi-scenario iterative robust optimization methodology for analog/mixed-signal circuits. We show that due to local circuit performance mono...
Yan Li, Vladimir Stojanovic