Aggressive voltage scaling to 1V and below through technology, circuit, and architecture optimization has been proven to be the key to ultra low-power design. The key technology t...
: In this paper we focus on the reduction of switching activity in combinational logic circuits. An algorithmic approach using k-map has been proposed which modifies the normal opt...
R. V. Menon, S. Chennupati, Naveen K. Samala, Damu...
In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA...
This paper considers the problems of admission control and virtual circuit routing in high performance computing and communication systems. Admission control and virtual circuit r...
Baruch Awerbuch, Rainer Gawlick, Frank Thomson Lei...
This paper presents a fast and scalable method of computing signal toggle rate in FPGA-based circuits. Our technique is a vectorless estimation technique, which can be used in a C...