1217 search results - page 85 / 244 » Uncertainty-aware circuit optimization |
GECCO
2007
Springer
15 years 5 months ago
2007
Springer
This paper shows that the evolutionary design of digital circuits which is conducted at the gate level is able to produce human-competitive circuits at the transistor level. In ad...
108
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CLEIEJ
2010
14 years 8 months ago
2010
A 3D circuit is the stacking of regular 2D circuits. The advances on the fabrication and packaging technologies allowed interconnecting stacked 2D circuits by using 3D vias. Howeve...
ICCAD
1997
IEEE
15 years 3 months ago
1997
IEEE
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends...
107
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DAC
2008
ACM
15 years 1 months ago
2008
ACM
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
—1As technology scales, the aging effect caused by Negative Bias Temperature Instability (NBTI) has become a major reliability concern for circuit designers. On the other hand, r...