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» Uncertainty-aware circuit optimization
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DAC
2005
ACM
16 years 7 days ago
Enhanced leakage reduction Technique by gate replacement
Input vector control (IVC) technique utilizes the stack effect in CMOS circuit to apply the minimum leakage vector (MLV) to the circuit at the sleep mode to reduce leakage. Additi...
Lin Yuan, Gang Qu
ICCAD
2001
IEEE
106views Hardware» more  ICCAD 2001»
15 years 8 months ago
A Layout-Aware Synthesis Methodology for RF Circuits
In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling a...
Peter J. Vancorenland, Geert Van der Plas, Michiel...
DFT
2008
IEEE
103views VLSI» more  DFT 2008»
15 years 5 months ago
Arbitrary Error Detection in Combinational Circuits by Using Partitioning
The paper presents a new technique for designing a concurrently checking combinational circuit. The technique is based on partitioning the circuit into two independent sub-circuit...
Osnat Keren, Ilya Levin, Vladimir Ostrovsky, Beni ...
GECCO
2004
Springer
120views Optimization» more  GECCO 2004»
15 years 4 months ago
Comparison of Selection Strategies for Evolutionary Quantum Circuit Design
Evolution of quantum circuits faces two major challenges: complex and huge search spaces and the high costs of simulating quantum circuits on conventional computers. In this paper ...
André Leier, Wolfgang Banzhaf
62
Voted
ICCAD
2000
IEEE
99views Hardware» more  ICCAD 2000»
15 years 3 months ago
Potential Slack: An Effective Metric of Combinational Circuit Performance
This paper proposes the concept of potential slack and show it is an effective metric of combinational circuit performance. We provide several methods for estimating potential sla...
Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh