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SPAA
2006
ACM
15 years 3 months ago
Modeling instruction placement on a spatial architecture
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
ISPD
2005
ACM
151views Hardware» more  ISPD 2005»
15 years 3 months ago
Thermal via placement in 3D ICs
As thermal problems become more evident, new physical design paradigms and tools are needed to alleviate them. Incorporating thermal vias into integrated circuits (ICs) is a promi...
Brent Goplen, Sachin S. Sapatnekar
WEBDB
2004
Springer
122views Database» more  WEBDB 2004»
15 years 2 months ago
Querying Bi-level Information
In our research on superimposed information management, we have developed applications where information elements in the superimposed layer serve to annotate, comment, restructure...
Sudarshan Murthy, David Maier, Lois M. L. Delcambr...
CAV
2008
Springer
122views Hardware» more  CAV 2008»
14 years 11 months ago
Thread Quantification for Concurrent Shape Analysis
In this paper we address the problem of shape analysis for concurrent programs. We present new algorithms, based on abstract interpretation, for automatically verifying properties ...
Josh Berdine, Tal Lev-Ami, Roman Manevich, G. Rama...
SPAA
2004
ACM
15 years 3 months ago
Cache-oblivious shortest paths in graphs using buffer heap
We present the Buffer Heap (BH), a cache-oblivious priority queue that supports Delete-Min, Delete, and Decrease-Key operations in O( 1 B log2 N B ) amortized block transfers fro...
Rezaul Alam Chowdhury, Vijaya Ramachandran