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» Understanding transactional memory performance
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PLDI
2010
ACM
15 years 2 months ago
A GPGPU compiler for memory optimization and parallelism management
This paper presents a novel optimizing compiler for general purpose computation on graphics processing units (GPGPU). It addresses two major challenges of developing high performa...
Yi Yang, Ping Xiang, Jingfei Kong, Huiyang Zhou
ICS
2005
Tsinghua U.
15 years 3 months ago
The implications of working set analysis on supercomputing memory hierarchy design
Supercomputer architects strive to maximize the performance of scientific applications. Unfortunately, the large, unwieldy nature of most scientific applications has lead to the...
Richard C. Murphy, Arun Rodrigues, Peter M. Kogge,...
IISWC
2008
IEEE
15 years 3 months ago
Temporal streams in commercial server applications
Commercial server applications remain memory bound on modern multiprocessor systems because of their large data footprints, frequent sharing, complex non-strided access patterns, ...
Thomas F. Wenisch, Michael Ferdman, Anastasia Aila...
SIGMETRICS
2011
ACM
178views Hardware» more  SIGMETRICS 2011»
14 years 4 months ago
Should we worry about memory loss?
In recent years the High Performance Computing (HPC) industry has benefited from the development of higher density multi-core processors. With recent chips capable of executing u...
O. Perks, Simon D. Hammond, S. J. Pennycook, Steph...
DATE
2003
IEEE
105views Hardware» more  DATE 2003»
15 years 2 months ago
Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation
: Stresses are considered an integral part of any modern industrial DRAM test. This paper describes a novel method to optimize stresses for memory testing, using defect injection a...
Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev...