70 search results - page 11 / 14 » Using Abstraction in the Verification of Simulation Coercion |
CAV
2009
Springer
15 years 10 months ago
2009
Springer
Abstract. When a model does not satisfy a given specification, a counterexample is produced by the model checker to demonstrate the failure. A user must then examine the counterexa...
DSD
2004
IEEE
15 years 1 months ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
TODAES
2008
14 years 9 months ago
2008
Abstract-- Automata-based methods for generating PSL hardware assertion checkers were primarily considered for use with temporal sequences, as opposed to full-scale properties. We ...
COOP
2004
14 years 11 months ago
2004
Abstract. The enormous improvements in the efficiency of model-checking techniques in recent years facilitates their application to ever more complex systems of concurrent and dist...
ISMVL
2007
IEEE
15 years 4 months ago
2007
IEEE
Designing modern circuits comprised of millions of gates is a very challenging task. Therefore new directions are investigated for efficient modeling and verification of such syst...