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HPCA
2005
IEEE
16 years 2 days ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
IPPS
2007
IEEE
15 years 6 months ago
Incorporating Latency in Heterogeneous Graph Partitioning
Parallel applications based on irregular meshes make use of mesh partitioners for efficient execution. Some mesh partitioners can map a mesh to a heterogeneous computational plat...
Eric E. Aubanel, Xiaochen Wu
CLUSTER
2002
IEEE
15 years 4 months ago
Shell over a Cluster (SHOC): Towards Achieving Single System Image via the Shell
With dramatic improvements in cost-performance, the use of clusters of personal computers is fast becoming widespread. For ease of use and management, a Single System Image (SSI) ...
C. M. Tan, C. P. Tan, Weng-Fai Wong
IISWC
2009
IEEE
15 years 6 months ago
SD-VBS: The San Diego Vision Benchmark Suite
—In the era of multi-core, computer vision has emerged as an exciting application area which promises to continue to drive the demand for both more powerful and more energy effi...
Sravanthi Kota Venkata, Ikkjin Ahn, Donghwan Jeon,...
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ISCA
2008
IEEE
148views Hardware» more  ISCA 2008»
15 years 6 months ago
Atomic Vector Operations on Chip Multiprocessors
The current trend is for processors to deliver dramatic improvements in parallel performance while only modestly improving serial performance. Parallel performance is harvested th...
Sanjeev Kumar, Daehyun Kim, Mikhail Smelyanskiy, Y...