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98
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DAC
1996
ACM
15 years 1 months ago
A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts
Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Pro...
Nguyen-Ngoc Bình, Masaharu Imai, Akichika S...
CORR
1999
Springer
116views Education» more  CORR 1999»
14 years 9 months ago
Efficient and Extensible Algorithms for Multi Query Optimization
Complex queries are becoming commonplace, with the growing use of decision support systems. These complex queries often have a lot of common sub-expressions, either within a singl...
Prasan Roy, S. Seshadri, S. Sudarshan, Siddhesh Bh...
ASYNC
1997
IEEE
103views Hardware» more  ASYNC 1997»
15 years 1 months ago
Efficient Timing Analysis Algorithms for Timed State Space Exploration
This paper presents new timing analysis algorithms for efficient state space exploration during timed circuit synthesis. Timed circuits are a class of asynchronous circuits that i...
Wendy Belluomini, Chris J. Myers
96
Voted
PAAMS
2010
Springer
14 years 7 months ago
A Case Study on Grammatical-Based Representation for Regular Expression Evolution
Abstract. Regular expressions, or simply regex, have been widely used as a powerful pattern matching and text extractor tool through decades. Although they provide a powerful and f...
Antonio González-Pardo, David F. Barrero, D...
GLVLSI
2003
IEEE
152views VLSI» more  GLVLSI 2003»
15 years 2 months ago
Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
Frank Grassert, Dirk Timmermann