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» Using Symbolic Simulation for Bounded Property Checking
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COMCOM
2004
110views more  COMCOM 2004»
14 years 11 months ago
On the latency and fairness characteristics of pre-order deficit round Robin
In the emerging high-speed packet-switched networks, fair packet scheduling algorithms in switches and routers will form an important component of the mechanisms that seek to sati...
Salil S. Kanhere, Harish Sethu
ESOP
2005
Springer
15 years 5 months ago
Asserting Bytecode Safety
Abstract. We instantiate an Isabelle/HOL framework for proof carrying code to Jinja bytecode, a downsized variant of Java bytecode featuring objects, inheritance, method calls and ...
Martin Wildmoser, Tobias Nipkow
JACM
2002
163views more  JACM 2002»
14 years 11 months ago
Formal verification of standards for distance vector routing protocols
We show how to use an interactive theorem prover, HOL, together with a model checker, SPIN, to prove key properties of distance vector routing protocols. We do three case studies: ...
Karthikeyan Bhargavan, Davor Obradovic, Carl A. Gu...
STACS
2005
Springer
15 years 5 months ago
Sampling Sub-problems of Heterogeneous Max-cut Problems and Approximation Algorithms
Abstract Abstract. Recent work in the analysis of randomized approximation algorithms for NP-hard optimization problems has involved approximating the solution to a problem by the ...
Petros Drineas, Ravi Kannan, Michael W. Mahoney
FMCAD
2006
Springer
15 years 3 months ago
Design for Verification of the PCI-X Bus
The importance of re-usable Intellectual Properties (IPs) cores is increasing due to the growing complexity of today's system-on-chip and the need for rapid prototyping. In th...
Haja Moinudeen, Ali Habibi, Sofiène Tahar