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SAMOS
2010
Springer
15 years 2 months ago
Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator
—Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-ti...
Igor Böhm, Björn Franke, Nigel P. Topham
DAC
2005
ACM
16 years 5 months ago
Approximate VCCs: a new characterization of multimedia workloads for system-level MpSoC design
System-level design methods specifically targeted towards multimedia applications have recently received a lot of attention. Multimedia workloads are known to have a high degree o...
Yanhong Liu, Samarjit Chakraborty, Wei Tsang Ooi
EMSOFT
2005
Springer
15 years 10 months ago
A unified HW/SW interface model to remove discontinuities between HW and SW design
One major challenge in System-on-Chip (SoC) design is the definition and design of interfaces between hardware and software. Traditional ASIC designer and software designer model ...
Aimen Bouchhima, Xi Chen, Frédéric P...
JTRES
2009
ACM
15 years 11 months ago
Avoiding unbounded priority inversion in barrier protocols using gang priority management
Large real-time software systems such as real-time Java virtual machines often use barrier protocols, which work for a dynamically varying number of threads without using centrali...
Harald Röck, Joshua S. Auerbach, Christoph M....
CODES
2000
IEEE
15 years 8 months ago
Towards a new standard for system-level design
—Huge new design challenges for system-on-chip (SoC) are the result of decreasing time-to-market coupled with rapidly increasing gate counts and embedded software representing 50...
Stan Y. Liao