259 search results - page 27 / 52 » Using Transformations and Verification in Circuit Design |
99
Voted
DAC
2004
ACM
16 years 1 months ago
2004
ACM
Circuits using nano-meter technologies are becoming increasingly vulnerable to signal interference from multiple noise sources as well as radiation-induced soft errors. One way to...
DAC
2000
ACM
16 years 1 months ago
2000
ACM
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...
136
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DAC
2010
ACM
15 years 3 months ago
2010
ACM
Effective system verification requires good specifications. The lack of sufficient specifications can lead to misses of critical bugs, design re-spins, and time-to-market slips. I...
DAC
2003
ACM
16 years 1 months ago
2003
ACM
Binary Decision Diagrams (BDDs) often fail to exploit sharing between Boolean functions that differ only in their support variables. In a memory circuit, for example, the function...
100
Voted
VLSID
2009
IEEE
16 years 1 months ago
2009
IEEE
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...