Sciweavers

1407 search results - page 21 / 282
» Using Use Cases in Executable Z
Sort
View
108
Voted
CASES
2006
ACM
15 years 6 months ago
An accurate and efficient simulation-based analysis for worst case interruption delay
This paper proposes an efficient method to analyze worst case interruption delay (WCID) of a workload running on modern microprocessors using a cycle accurate simulator (CAS). Our...
Hiroshi Nakashima, Masahiro Konishi, Takashi Nakad...
RTCSA
1999
IEEE
15 years 6 months ago
Pipeline Timing Analysis Using a Trace-Driven Simulator
In this paper we present a technique for Worst-Case Execution Time WCET analysis for pipelined processors. Our technique uses a standard simulator instead of special-purpose pipel...
Jakob Engblom, Andreas Ermedahl
WSC
2000
15 years 3 months ago
Parallel execution of a sequential network simulator
Parallel discrete event simulation (PDES) techniques have not yet made a substantial impact on the network simulation community because of the need to recast the simulation models...
Kevin G. Jones, Samir Ranjan Das
SOQUA
2004
15 years 3 months ago
Scenario-based Component Testing Using Embedded Metadata
We present an approach for the use case and scenario-based testing of software components. Use cases and scenarios are applied to describe the functional requirements of a software...
Mark Strembeck, Uwe Zdun
DSN
2005
IEEE
15 years 8 months ago
A Wavefront Parallelisation of CTMC Solution Using MTBDDs
In this paper, we present a parallel implementation for the steady-state analysis of continuous-time Markov chains (CTMCs). This analysis is performed via solution of a linear equ...
Yi Zhang, David Parker, Marta Z. Kwiatkowska