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ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
12 years 12 months ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar
DATE
2009
IEEE
189views Hardware» more  DATE 2009»
15 years 4 months ago
CUFFS: An instruction count based architectural framework for security of MPSoCs
—Multiprocessor System on Chip (MPSoC) architecture is rapidly gaining momentum for modern embedded devices. The vulnerabilities in software on MPSoCs are often exploited to caus...
Krutartha Patel, Sri Parameswaran, Roshan G. Ragel
MICRO
2008
IEEE
136views Hardware» more  MICRO 2008»
15 years 3 months ago
Power to the people: Leveraging human physiological traits to control microprocessor frequency
Any architectural optimization aims at satisfying the end user. However, modern architectures execute with little to no knowledge about the individual user. If architectures could...
Alex Shye, Yan Pan, Benjamin Scholbrock, J. Scott ...
GECCO
2004
Springer
145views Optimization» more  GECCO 2004»
15 years 2 months ago
Search Based Automatic Test-Data Generation at an Architectural Level
Abstract. The need for effective testing techniques for architectural level descriptions is widely recognised. However, due to the variety of domain-specific architectural descript...
Yuan Zhan, John A. Clark
ROBOCUP
2004
Springer
133views Robotics» more  ROBOCUP 2004»
15 years 2 months ago
Towards a League-Independent Qualitative Soccer Theory for RoboCup
The paper discusses a top-down approach to model soccer knowledge, as it can be found in soccer theory books. The goal is to model soccer strategies and tactics in a way that they ...
Frank Dylla, Alexander Ferrein, Gerhard Lakemeyer,...