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FPL
2010
Springer
155views Hardware» more  FPL 2010»
14 years 7 months ago
Design and Implementation of Real-Time Transactional Memory
Transactional memory is a promising, optimistic synchronization mechanism for chip-multiprocessor systems. The simplicity of atomic sections, instead of using explicit locks, is al...
Martin Schoeberl, Peter Hilber
IPPS
2007
IEEE
15 years 3 months ago
Power-Aware Speedup
Power-aware processors operate in various power modes to reduce energy consumption with a corresponding decrease in peak processor throughput. Recent work has shown power-aware cl...
Rong Ge, Kirk W. Cameron
97
Voted
CASES
2008
ACM
14 years 11 months ago
Compiling custom instructions onto expression-grained reconfigurable architectures
While customizable processors aim at combining the flexibility of general purpose processors with the speed and power advantages of custom circuits, commercially available process...
Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi
SIGIR
2009
ACM
15 years 4 months ago
Dynamicity vs. effectiveness: studying online clustering for scatter/gather
We proposed and implemented a novel clustering algorithm called LAIR2, which has constant running time average for on-the-fly Scatter/Gather browsing [4]. Our experiments showed ...
Weimao Ke, Cassidy R. Sugimoto, Javed Mostafa
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
15 years 1 months ago
Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology
This paper presents an environment based on SystemC for architecture specification of programmable systems. Making use of the new architecture description language ArchC, able to ...
Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Aze...