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IPPS
2007
IEEE
14 years 21 days ago
Load Miss Prediction - Exploiting Power Performance Trade-offs
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
Konrad Malkowski, Greg M. Link, Padma Raghavan, Ma...
ISLPED
2005
ACM
86views Hardware» more  ISLPED 2005»
13 years 12 months ago
An evaluation of code and data optimizations in the context of disk power reduction
Disk power management is becoming increasingly important in high-end server and cluster type of environments that execute dataintensive applications. While hardware-only approache...
Mahmut T. Kandemir, Seung Woo Son, Guangyu Chen
INFOCOM
2009
IEEE
14 years 1 months ago
Rateless Coding with Feedback
The erasure resilience of rateless codes, such as Luby-Transform (LT) codes, makes them particularly suitable to a wide variety of loss-prone wireless and sensor network applicati...
Andrew Hagedorn, Sachin Agarwal, David Starobinski...
IPPS
2008
IEEE
14 years 24 days ago
Reducing wasted resources to help achieve green data centers
In this paper we introduce a new approach to the consolidation strategy of a data center that allows an important reduction in the amount of active nodes required to process a het...
Jordi Torres, David Carrera, Kevin Hogan, Ricard G...
ISCA
2009
IEEE
318views Hardware» more  ISCA 2009»
14 years 1 months ago
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
Abhishek Bhattacharjee, Margaret Martonosi