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CODES
2007
IEEE
15 years 3 months ago
Performance modeling for early analysis of multi-core systems
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittman...
ISPASS
2008
IEEE
15 years 3 months ago
Configurational Workload Characterization
Although the best processor design for executing a specific workload does depend on the characteristics of the workload, it can not be determined without factoring-in the effect o...
Hashem Hashemi Najaf-abadi, Eric Rotenberg
CF
2010
ACM
15 years 2 months ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
HICSS
2009
IEEE
155views Biometrics» more  HICSS 2009»
15 years 4 months ago
Collaborative Recommender Systems for Building Automation
Building Automation Systems (BASs) can save building owners money by reducing energy consumption while simultaneously preserving occupant comfort. There are algorithms that optimi...
Michael LeMay, Jason J. Haas, Carl A. Gunter
MICRO
2009
IEEE
103views Hardware» more  MICRO 2009»
15 years 4 months ago
BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware support
A platform that supported Sequential Consistency (SC) for all codes — not only the well-synchronized ones — would simplify the task of programmers. Recently, several hardware ...
Wonsun Ahn, Shanxiang Qi, M. Nicolaides, Josep Tor...