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» Using the Temporal Logic RDL for Design Specifications
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CLEIEJ
2006
88views more  CLEIEJ 2006»
14 years 9 months ago
A Stochastic Concurrent Constraint Based Framework to Model and Verify Biological Systems
Concurrent process calculi are powerful formalisms for modelling concurrent systems. The mathematical style underlying process calculi allow to both model and verify properties of...
Carlos Olarte, Camilo Rueda
CJ
2010
80views more  CJ 2010»
14 years 9 months ago
Verifying a Synthesized Implementation of IEEE-754 Floating-Point Exponential Function using HOL
rder logic (HOL) theorem prover. The high ability of abstraction in the HOL verification system allows its use for the verification task over the whole design path of the circuit, ...
Behzad Akbarpour, Amr T. Abdel-Hamid, Sofiè...
DAC
1996
ACM
15 years 1 months ago
A Register File and Scheduling Model for Application Specific Processor Synthesis
In this paper, we outline general design steps of our synthesis tool to realize application specific co-processors such that for a given scientific application having intensive ite...
Ehat Ercanli, Christos A. Papachristou
CODES
2002
IEEE
15 years 2 months ago
Codesign-extended applications
We challenge the widespread assumption that an embedded system’s functionality can be captured in a single specification and then partitioned among software and custom hardware ...
Brian Grattan, Greg Stitt, Frank Vahid
GIS
2006
ACM
15 years 10 months ago
Analyzing theme, space, and time: an ontology-based approach
The W3C's Semantic Web Activity is illustrating the use of semantics for information integration, search, and analysis. However, the majority of the work in this community ha...
Matthew Perry, Farshad Hakimpour, Amit P. Sheth