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ASAP
2007
IEEE
169views Hardware» more  ASAP 2007»
15 years 4 months ago
Reduced Delay BCD Adder
Financial and commercial applications use decimal data and spend most of their time in decimal arithmetic. Software implementation of decimal arithmetic is typically at least 100 ...
A. A. Bayrakci, A. Akkas
86
Voted
IPPS
2007
IEEE
15 years 4 months ago
A Study of Design Efficiency with a High-Level Language for FPGAs
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
Zain-ul-Abdin, Bertil Svensson
ICMCS
2006
IEEE
194views Multimedia» more  ICMCS 2006»
15 years 3 months ago
An Architecture Design of Threshold-Based Best-Basis Algorithm
The best-basis algorithm has gained much importance on textured-based image compression and denoising of signals. In this paper, an architecture for the wavelet-packet based best-...
S. Mayilavelane Aroutchelvame, Kaamran Raahemifar
ISCAS
2006
IEEE
74views Hardware» more  ISCAS 2006»
15 years 3 months ago
NIUGAP: low latency network interface architecture with Gray code for networks-on-chip
— The implementation of a high-performance network-on-chip (NoC) requires an efficient design for the network interface unit (NIU) that connects the switched network to the IP c...
Daewook Kim, Manho Kim, Gerald E. Sobelman
100
Voted
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
15 years 3 months ago
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi,...