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FDL
2004
IEEE
15 years 1 months ago
The Formal Simulation Semantics of SystemVerilog
We present a rigorous but transparent semantics definition of SystemVerilog that covers processes with blocking and non-blocking statements as well as their interaction with the s...
Martin Zambaldi, Wolfgang Ecker, T. Kruse, W. M&uu...
71
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DDECS
2006
IEEE
140views Hardware» more  DDECS 2006»
15 years 1 months ago
A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming
Abstract-- Genetic Parallel Programming (GPP) evolves parallel programs for MIMD architectures with multiple arithmetic/logic processors (MAPs). This paper describes a tool intende...
Zbysek Gajda
FDL
2006
IEEE
15 years 1 months ago
Verification-Oriented Behavioral Modeling of Non-Linear Analog
In this work, an approach to the `verification-oriented' modeling of the analog parts' behavior of mixed-signal circuits is presented. Starting from a continuous-time, c...
Martin Freibothe, Jens Doege, Torsten Coym, Stefan...
FPL
2006
Springer
208views Hardware» more  FPL 2006»
15 years 1 months ago
Implementation in Fpgas of Jacobi Method to Solve the Eigenvalue and Eigenvector Problem
This work shows a modular architecture based on FPGA's to solve the eigenvalue problem according to the Jacobi method. This method is able to solve the eigenvalues and eigenv...
Ignacio Bravo, Pedro Jiménez, Manuel Mazo, ...
ISSS
1995
IEEE
109views Hardware» more  ISSS 1995»
15 years 1 months ago
1995 high level synthesis design repository
In this paper we brie y describe a set of designs that can serve as examples for High Level Synthesis (HLS) systems. The designs vary in complexity from simple behavioral nite st...
Preeti Ranjan Panda, Nikil D. Dutt