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78
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DATE
2000
IEEE
108views Hardware» more  DATE 2000»
15 years 2 months ago
A 50 Mbit/s Iterative Turbo-Decoder
Very low bit error rate has become an important constraint in high performance communication systems that operate at very low signal to noise ratios: due to their impressive codin...
F. Viglione, Guido Masera, Gianluca Piccinini, Mas...
ICPP
1999
IEEE
15 years 1 months ago
Adaptive Bubble Router: A Design to Improve Performance in Torus Networks
A router design for torus networks that significantly reduces message latency over traditional wormhole routers is presented in this paper. This new router implements virtual cut-...
Valentin Puente, Ramón Beivide, José...
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
15 years 1 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
64
Voted
MSE
1999
IEEE
118views Hardware» more  MSE 1999»
15 years 1 months ago
Training IP Creators and Integrators
Intellectual property IP blocks are being created for reuse and marketed as a means of reducing the development time of complex designs. This in turn leads to a reduction in time ...
Donald W. Bouldin, Senthil Natarajan, Benjamin A. ...
DATE
1998
IEEE
116views Hardware» more  DATE 1998»
15 years 1 months ago
VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform
This paper presents a VLSI Architecture to implement the forward and inverse 2-D Discrete Wavelet Transform (FDWT/IDWT), to compress medical images for storage and retrieval. Loss...
Isidoro Urriza, José I. Artigas, José...