2449 search results - page 106 / 490 » VLSI |
153
Voted
ISPD
1998
ACM
15 years 8 months ago
1998
ACM
As chip size and design density increase, coupling effects (crosstalk) between signal wires become increasingly critical to on–chip timing and even functionality. A method is pr...
122
Voted
DAC
1997
ACM
15 years 7 months ago
1997
ACM
In this paper, we present a new hypergraph partitioning algorithm that is based on the multilevel paradigm. In the multilevel paradigm, a sequence of successively coarser hypergra...
145
Voted
ICCAD
1996
IEEE
15 years 7 months ago
1996
IEEE
In this paper, we present a new capacitance extraction method named Dimension Reduction Technique (DRT) for 3D VLSI interconnects. The DRT converts a complex 3D problem into a ser...
128
Voted
ICCAD
1996
IEEE
15 years 7 months ago
1996
IEEE
Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However,for typical R...
108
Voted
ICCD
1993
IEEE
15 years 7 months ago
1993
IEEE
In this paper the design of a high-speed cryptographic coprocessor is presented. This coprocessor is named Subterranean and can be used for both cryptographic pseudorandom sequenc...