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DAC
1997
ACM
15 years 8 months ago
Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...
Howard H. Chen, David D. Ling
107
Voted
ICANN
1997
Springer
15 years 8 months ago
Analog Sequential Architecture for Neuro-Fuzzy Models VLSI Implementation
Juan Manuel Moreno, Jordi Madrenas, Eduard Alarc&o...
97
Voted
DAC
1996
ACM
15 years 8 months ago
iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips
In this paper, we present the rst chip-level electrothermal simulator, iCET. For a given chip layout, packaging material, user-speci ed input signal patterns, and thermal boundar...
Yi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury...
DAC
1996
ACM
15 years 8 months ago
A Probability-Based Approach to VLSI Circuit Partitioning
Iterative-improvement 2-way min-cut partitioning is an important phase in most circuit partitioning tools. Most iterative improvement techniques for circuit netlists like the Fidd...
Shantanu Dutt, Wenyong Deng
130
Voted
DAC
1996
ACM
15 years 8 months ago
Symphony: A Simulation Backplane for Parallel Mixed-Mode Co-Simulation of VLSI Systems
In this paper we present an integrated simulation paradigm in which parallel mixed-mode co-simulation is accomplished by integrating sequential simulators in a software simulation ...
Antonio R. W. Todesco, Teresa H. Y. Meng