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VLSI
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Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware
15 years 7 months ago
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Benjamin A. Levine, R. Reed Taylor, Herman Schmit
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Interfacing Reconfigurable Logic with a CPU
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Kip Walker, Mihai Budiu, Seth Copen Goldstein
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GLVLSI
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Low power and high performance design challenges in future technologies
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Vivek De, Shekhar Borkar
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High-performance bidirectional repeaters
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Sudhakar Bobba, Ibrahim N. Hajj
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Measuring routing congestion for multi-layer global routing
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Tom W. Chen, Alkan Cengiz
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