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VLSID
2010
IEEE
211views VLSI» more  VLSID 2010»
15 years 8 months ago
A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM
A novel design approach for simultaneous power and stability (static noise margin, SNM) optimization of nanoCMOS static random access memory (SRAM) is presented. A 45nm single-end...
Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dh...
VLSID
2010
IEEE
155views VLSI» more  VLSID 2010»
15 years 8 months ago
Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore
Abstract—Microfluidics-based biochips are revolutionizing highthroughput sequencing, parallel immunoassays, clinical diagnostics, and drug discovery. These devices enable the pre...
Krishnendu Chakrabarty
FCCM
2009
IEEE
123views VLSI» more  FCCM 2009»
15 years 8 months ago
Scalable High Throughput and Power Efficient IP-Lookup on FPGA
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmab...
Hoang Le, Viktor K. Prasanna
FCCM
2009
IEEE
106views VLSI» more  FCCM 2009»
15 years 8 months ago
Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators
Modern use of FPGAs as hardware accelerators involves the partial reconfiguration of hardware resources as the application executes. In this paper, we present a polynomial time al...
Joon Edward Sim, Weng-Fai Wong, Jürgen Teich
FCCM
2009
IEEE
316views VLSI» more  FCCM 2009»
15 years 8 months ago
An FPGA Implementation for Solving Least Square Problem
This paper proposes a high performance least square solver on FPGAs using the Cholesky decomposition method. Our design can be realized by iteratively adopting a single triangular...
Depeng Yang, Gregory D. Peterson, Husheng Li, Junq...