2449 search results - page 211 / 490 » VLSI |
126
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DFT
2009
IEEE
15 years 7 months ago
2009
IEEE
We present an error detection technique for a floating point adder which uses a checker adder of reduced precision to determine if the result is correct within some error bound. O...
198
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DFT
2009
IEEE
15 years 7 months ago
2009
IEEE
Optimizing the BIST configuration based on the characteristics of the design under test is a complicated and challenging work for test engineers. Since this problem has multiple o...
140
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GLVLSI
2010
IEEE
15 years 6 months ago
2010
IEEE
For timing-driven or yield-driven designs, non-tree routing has become more and more popular and additional loops provide the redundant paths to protect against the effect of the ...
135
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GLVLSI
2007
IEEE
15 years 6 months ago
2007
IEEE
Nanoscale crossbars built from nanowires can form high density memories and programmable logic devices. To integrate such nanoscale devices with other circuits, nanowire decoders ...
154
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DFT
2008
IEEE
15 years 6 months ago
2008
IEEE
This paper addresses a new threat to the security of integrated circuits (ICs). The migration of IC fabrication to untrusted foundries has made ICs vulnerable to malicious alterat...