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VTS
2008
IEEE
70views Hardware» more  VTS 2008»
16 years 5 days ago
A Statistical Approach to Characterizing and Testing Functionalized Nanowires
Unlike the top-down photolithographic CMOS VLSI process, cost-effective bulk fabrication of nanodevices calls for a bottom-up approach, generally called self-assembly. Selfassembl...
James Dardig, Haralampos-G. D. Stratigopoulos, Eri...
GLVLSI
2007
IEEE
135views VLSI» more  GLVLSI 2007»
16 years 4 days ago
Exact sat-based toffoli network synthesis
Compact realizations of reversible logic functions are of interest in the design of quantum computers. Such reversible functions are realized as a cascade of Toffoli gates. In th...
Daniel Große, Xiaobo Chen, Gerhard W. Dueck,...
GLVLSI
2007
IEEE
167views VLSI» more  GLVLSI 2007»
16 years 4 days ago
A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS
A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a new approach to multi-level synthesis for PAL-based CP...
Dariusz Kania
GLVLSI
2007
IEEE
187views VLSI» more  GLVLSI 2007»
16 years 4 days ago
DAG based library-free technology mapping
This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through t...
Felipe S. Marques, Leomar S. da Rosa Jr., Renato P...
GLVLSI
2007
IEEE
328views VLSI» more  GLVLSI 2007»
16 years 4 days ago
New timing and routability driven placement algorithms for FPGA synthesis
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong H...