2449 search results - page 261 / 490 » VLSI |
147
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ARVLSI
1995
IEEE
15 years 9 months ago
1995
IEEE
This paper presents an architecture for generating a high-speed data pattern with precise edge placement resolution by using the matched delay technique. The technique involves ...
153
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GLVLSI
2010
IEEE
15 years 8 months ago
2010
IEEE
This paper describes a physics-based semi-analytical model for Schottky-barrier carbon nanotube (CNT) and graphene nanoribbon (GNR) transistors. The model includes the treatment o...
150
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GLVLSI
2010
IEEE
15 years 8 months ago
2010
IEEE
As the rated performance of microprocessors increases, voltage droop emergencies become a significant problem. In this paper, two new techniques to combat voltage droop emergencie...
177
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GLVLSI
2010
IEEE
15 years 8 months ago
2010
IEEE
Loop caches provide an effective method for decreasing memory hierarchy energy consumption by storing frequently executed code in a more energy efficient structure than the level ...
184
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DFT
2006
IEEE
15 years 8 months ago
2006
IEEE
As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. ...