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DATE
1997
IEEE
115views Hardware» more  DATE 1997»
15 years 10 months ago
Analogue layout generation by World Wide Web server-based agents
A World Wide Web (WWW) based client/server system has been developed which allows server-side process independent layout generators to generate the design rule correct geometry of...
Les T. Walczowski, D. Nalbantis, W. A. J. Waller, ...
DATE
1997
IEEE
86views Hardware» more  DATE 1997»
15 years 10 months ago
Highly scalable parallel parametrizable architecture of the motion estimator
In this paper a parametrizable architecture of a motion estimator (ME) is presented. The ME is designed as a generic full pixel calculation module which can be adopted for di eren...
Radim Cmar, Serge Vernalde
ICCAD
1996
IEEE
129views Hardware» more  ICCAD 1996»
15 years 10 months ago
Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits
-- In this tutorial we discuss concepts and techniques for the accurate and efficient modeling and extraction of interconnect parasitics in VLSI designs. Due toincreasing operating...
N. P. van der Meijs, T. Smedes
DAC
1996
ACM
15 years 10 months ago
Hot-Carrier Reliability Enhancement via Input Reordering and Transistor Sizing
Hot-carrier eects and electromigration are the two important failure mechanisms that signi cantly impact the long-term reliability of high-density VLSI ICs. In this paper, we prese...
Aurobindo Dasgupta, Ramesh Karri
ITC
1993
IEEE
104views Hardware» more  ITC 1993»
15 years 10 months ago
A BIST Scheme for an SNR Test of a Sigma-Delta ADC
Built-In-Self-Test BIST for VLSI systems is desirable in order to reduce the cost per chip of production-time testing by the manufacturer. In addition, it can provide the means ...
M. F. Toner, Gordon W. Roberts