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VLSID
2003
IEEE
253views VLSI» more  VLSID 2003»
16 years 5 months ago
High Level Synthesis from Sim-nML Processor Models
The design of modern complex embedded systems require a high level of abstraction of the design. The SimnML[1] is a specification language to model processors for such designs. Se...
Souvik Basu, Rajat Moona
VLSID
2003
IEEE
104views VLSI» more  VLSID 2003»
16 years 5 months ago
Analyzing Soft Errors in Leakage Optimized SRAM Design
Reducing leakage power and improving the reliability of data stored in the memory cells are both becoming challenging as technology scales down. While the smaller threshold voltag...
Vijay Degalahal, Narayanan Vijaykrishnan, Mary Jan...
VLSID
2003
IEEE
144views VLSI» more  VLSID 2003»
16 years 5 months ago
The Impact of Bit-Line Coupling and Ground Bounce on CMOS SRAM Performance
In this paper, we provide an analytical framework to study the inter-cell and intra-cell bit-line coupling when it is superimposed with the ground bounce effect and show how those...
Li Ding 0002, Pinaki Mazumder
VLSID
2003
IEEE
96views VLSI» more  VLSID 2003»
16 years 5 months ago
Design Of A Universal BIST (UBIST) Structure
This paper introduces a Built-In Self Test (BIST) structure referred to as Universal BIST (UBIST). The Test Pattern Generator (TPG) of the proposed UBIST is designed to generate an...
Sukanta Das, Niloy Ganguly, Biplab K. Sikdar, Pari...
VLSID
2003
IEEE
115views VLSI» more  VLSID 2003»
16 years 5 months ago
An Adaptive Supply-Voltage Scheme for Low Power Self-Timed CMOS Digital Design
This paper combines an adaptive supply-voltage scheme with self-timed CMOS digital design, to achieve low power performance. The supply-voltage automatically tracks the input data...
W. Kuang, J. S. Yuan