2449 search results - page 327 / 490 » VLSI |
139
Voted
ASPDAC
2006
ACM
15 years 11 months ago
2006
ACM
- Power consumption is one of the major challenges in VLSI Design. Power constrained designs need tools to accurately predict the power consumption and provide feedback to designer...
131
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ASPDAC
2006
ACM
15 years 11 months ago
2006
ACM
- Traditionally, minimum possible area of a VLSI layout is considered the best for delay and power minimization due to decreased interconnect capacitance. This paper shows however ...
129
Voted
ASPDAC
2006
ACM
15 years 11 months ago
2006
ACM
Statistical timing analysis has been widely applied to predict the timing yield of VLSI circuits when process variations become significant. Existing statistical latch timing met...
156
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ASAP
2005
IEEE
15 years 10 months ago
2005
IEEE
We studied the dynamic instruction count reduction for a single-thread, vectorized and a multi-threaded, non-vectorized, MPEG-4 video encoder. Results indicate a maximum improveme...
131
Voted
CEC
2005
IEEE
15 years 10 months ago
2005
IEEE
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...